How Semiconductor DRAM Went 3D



Note: I should clarify that the first Intel 1103 was not a Dennard 1-transistor design. It had 3 transistors, and eventually hit the …

22 Comments

  1. DRAM reads are not destructive like core reads, they simply rely on the gate charge to keep the bit transistor on when you look at it. Refresh is needed because you can never get leakage current to zero so after a while all the charge bleeds out. We saw this in an error in cell phone code where the self refresh was not enabled in time when the proc went to sleep so the memory just bled out and the phone crashed: For standby, the proc was no longer reading or refreshing memory so the chips had a commad that allowed them to do that independently.

  2. I wonder if someone is checking the accuracy of your videos. I'm a business teacher,and I'm hearing everything you say for the first time, I have no idea if you have any inaccuracies. Do you have any critics on YouTube and have you listened to their work? Do they (if any) give you useful feedback?

  3. ICs have always been about shrinking the electronic component to the smallest it can possibly be. Sure, transistors are what comprise processors, but capacitors have to be even smaller for ram.

  4. The "high-k" dielectric don't seem that impressive with a k of (according to this video) 25 maximum, compared to for example barium titanate, which can have up to 15,000. However I guess the materials that can be used in DRAM are very much limited by the manufacturing process.

  5. This documentary is your best work by far ❀

    Fusion of electron microscope images and explanation is something else, I’m learning physics more than business

  6. Love seeing DRAM makers getting some respect for their mind-bending process technologies. Unfortunately, DRAM often gets short shrift because it’s seen as “lagging” in process technology behind the leading edge logic guys, because they’re not making, as you mentioned, transistors like FinFETs, and because DRAM is a commodity where cost is king.

    However, as you explained, DRAM first went to 3D capacitor structures, which greatly increased manufacturing complexity. But by the mid-2000s (5+ years before FinFETs became a thing), DRAM makers also started making 3D transistors as well. The Access Device (AD) transistor used to be a planar nMOSFET. Hundreds of ADs would be lined up next to each other, then the Wordline was a piece of metal (or poly or whatever) that was laid over all of the ADs in the same row, forming the Gate of all AD, such that when the Wordline is activated, all of the ADs connected to that Wordline are simultaneously turned on.

    In logic chips, the most important characteristic of a transistor is the switching speed, followed by things like on-current and off-current. In a DRAM Acess Device transistor, the single most important characteristic is minimizing rhe off-current (or I-Off), because that is what prevents capacitor leakage. So, by the mid-2000s, the channel length of the AD was getting to be too short, and I-Off couldn’t be kept small enough to prevent capacitor leakage. Similar amounts of leakage in a logic chip was “fine”, because it only increased power consumption slightly. But in DRAM it was devastating because the whole point of DRAM is to store data without forgetting it.

    So, that’s when DRAM Access Devices went 3D. But, they did the opposite of FinFETs, in that in DRAM, the Wordline was buried down into the silicon into a trench. Unlike the “trench capacitor”, which was actually just a punched out hole in the Si, buried Wordline is a true trench – a long, skinny, U-shaped trench filled with metal, etched into the Si between the Sources and Drains of the ADs. Hundreds of ADs are formed on a single buried Wordline, and of course there are millions of Wordlines per chip. Now with a buried Wordline, the channel that forms between the Source and Drain has to form under the same Wordline, in a long U-shape going through the silicon substrate. In the manner, the lateral distance between the Source and Drain can continue to shrink (which is required to continue die-shrinks), but the “effective channel length”, which is the total length of the channel as it wraps around the buried Wordline, can remain long. This long channel is what’s critical in stopping leakage when the AD is turned off. It’s also one reason why the switching speed is the AD is slow, relative to logic transistors.

    Anyway, you could do a whole separate video of the evolution of DRAM Access Device transistor technology. The combination of incredibly complex Acess Device and Capacitor technology are what allow us to have monolithic 4GB DRAM dies now, still still latencies less than 20ns

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